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A 40 Gb/s low-power analog equalizer has been realized in 0.13 mum CMOS technology. To achieve a peaking gain of 10 dB at 20 GHz and low power dissipation, an inductive feedback stage is proposed. This inductive feedback stage consumes 3.6 mW from a 1.2 V supply and the whole equalizer consumes 14.4 mW. The chip occupies 0.57 times 0.44 mm2. For a 40 Gb/s PRBS of 27-1, the measured BER is less than...
In this paper, a high-speed and low-power analog equalizer for a 40-inch trace on FR4 board has been realized in 0.18-mum CMOS technology. In order to achieve the low-power purpose and compensate the large signal attenuation of the FR4 trace simultaneously, the equalizer is presented by using the proposed RLC passive filter. This passive filter is used to obtain an additional peaking at high frequencies...
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