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Thread Level Speculation (TLS) and Transactional Memory (TM) have been proposed and developed to solve the difficulty of parallel programming during the last decades. Even though researchers have make effort to optimize these two kinds of systems for a long time, TLS and TM still have not been largely applied in commercial fields due to their wobbly performance. As we know, these two systems will...
Composable Multi-processors employ large instruction windows and distributed layout, both of which amplify the branch misprediction penalty. Once branch misprediction is detected, hundreds or thousands of instructions may be in flight. Simple squashing all the instructions following the mispredicted branch turn to be a large waste. Branch misprediction becomes the key bottleneck in these systems....
Cache size is a scarce resource in multi processors systems, Scheduling has a dramatic impact on the delay introduced by cache contention. This paper investigates the effects between programs running on a multi processors system, considering cache contention. This paper is proposed in low load case, the most programs' number of each core is one. The goal is to reduce cache contention between threads,...
This paper presents an approach for comparing various feature ranking (FR) methods. First, six classification benchmarks are created using Exhaustive Search (ES) to select the best feature subsets. The subset selections have been done within double (nested) cross-validation procedures guaranteeing realistic accuracy predictions to unseen examples. Next, seven filter FR approaches are compared and...
Applications of different categories contain varying levels of data, instruction and thread-level parallelism inherently. It's important to explore the potential coarse-grain thread-level parallelism in different applications to guide the computing resources allocation problem in multicore chips. Up to now, lots of depth researches have been mainly concentrated in the desktop applications. In order...
Thread level speculation (TLS) and transactional memory (TM) are both proposed to address the problem of productivity in multi-core era. Both of them require similar underlying support. In this paper, we propose a low-design-complexity approach to effective unified support for both TLS & TM, by extending a scalable TM model to support TLS. The baseline TM model chosen is LogTM. A distributed hardware...
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