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Most modern field-programmable gate arrays (FPGAs) employ a look-up table (LUT) as their basic logic cell. Although a k-input LUT can implement any k-input logic, its functionality relies on a large amount of configuration memory. As FPGA scales improve, the increased quantity of configuration memory cells required for FPGAs will require a larger area and consume more power. Moreover, the soft-error...
In recent years, as the VLSI process scale had been developed into deep sub-micro dimension, the problem of the routing delay becomes critical. Especially for reconfigurable logic devices (RLDs) like Field Programmable Gate Arrays (FPGAs), the routing resources occupy approximately 90% of area and delay performance. In this paper, we propose a novel 3D routing architecture based on building 3D connections...
As the size of integrated circuit has reached the nanoscale, embedded memories are more sensitive to single event upset (SEU), because of their low threshold voltage. In particular field-programmable gate arrays (FPGAs), which contain large amounts of configuration memories to implement customer circuits, are more likely to suffer from soft errors caused by SEU. In this research, we first develop...
We propose a variable grain logic cell (VGLC) architecture. Its key feature is variable granularity which helps to create a balance between two types of devices: coarse-grain type and fine-grain type. Because of this, the VGLC can achieved high-performance on any applications. In this paper, we describe the VGLC prototype chip designed in e-Shuttle 65nm library. In addition, in order to implement...
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