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The test vehicle is the FCOB with the chip size of 4mm*4mm*0.52mm, 0.32mm pitch and an I/O array of 13*13. Different solder height and UBM height are considered. The analysis is performed by a 2-D plane strain finite element model using Ansys 10.0 software. The Sn-3.5Ag solders are examined for their reliability by accelerated thermal cycling test with temperatures ranging from -40°C to 125°C. Two...
This paper reports a hermetic MEMS package structure with silicon wafer as bonded cap at wafer-level scale. CMP followed by spraying chemical smoothing process is utilized to thin the N(100) silicon cap wafer to the thickness of 150 mum after wafer-level Cu/Sn isothermal solidification bonding. Method for the thinning process and parameters for Cu/Sn isothermal solidification bonding process are researched...
In this paper, a wafer-level package with simultaneous through silicon via (TSV) connection and cavity hermetic sealing by low-temperature solder bonding for microelectromechanical system (MEMS) device such as resonator is presented. Wet etching technique combined with dry etching technique is utilized to achieve a ldquoY-shapedrdquo through wafer interconnection structure to shorten the TSV in order...
Due to the advantages of small-footprint, short-lead, high performance, high-packaging-density and thin profile, flip-chip-on-board (FCOB) technology is becoming an attractive choice in todaypsilas high density electronic packaging industry. With the trend toward lead-free and miniaturization in consumer electronics, the fatigue reliability of the small size lead-free FC solder joint on low cost PCB...
Sub 100 micron lead-free solder bumping and its related interconnection & reliability is becoming one of the important issues in today's electronic packaging industry. In this paper, a SnAg solder bumping area-array of 13 times 13 with the bump size less than 100mum on the TiW/Cu UBM was investigated. Bumps with smooth and shiny surface of 70mum in the height 90mum in the diameter were fabricated...
This paper introduces a novel wafer-level hermetic packaging technology for MEMS based on Cu/Sn isothermal solidification (IS) technology. We designed the structure of the intermediate multilayer and the pattern of sealing rings, optimized the bonding process, and analyzed some key factors affecting the hermeticity, such as the dimension of the sealing rings. Successful Cu/Sn IS bonding was realized...
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