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This paper reports a hermetic MEMS package structure with silicon wafer as bonded cap at wafer-level scale. CMP followed by spraying chemical smoothing process is utilized to thin the N(100) silicon cap wafer to the thickness of 150 mum after wafer-level Cu/Sn isothermal solidification bonding. Method for the thinning process and parameters for Cu/Sn isothermal solidification bonding process are researched...
Sub 100 micron lead-free solder bumping and its related interconnection & reliability is becoming one of the important issues in today's electronic packaging industry. In this paper, a SnAg solder bumping area-array of 13 times 13 with the bump size less than 100mum on the TiW/Cu UBM was investigated. Bumps with smooth and shiny surface of 70mum in the height 90mum in the diameter were fabricated...
This paper introduces a novel wafer-level hermetic packaging technology for MEMS based on Cu/Sn isothermal solidification (IS) technology. We designed the structure of the intermediate multilayer and the pattern of sealing rings, optimized the bonding process, and analyzed some key factors affecting the hermeticity, such as the dimension of the sealing rings. Successful Cu/Sn IS bonding was realized...
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