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This paper proposes an efficient method to predict the lifetime yield of analog circuits considering the joint effects of manufacturing process variations and parameter lifetime degradations. The method uses the idea of worst-case distance, which is an indicator of circuit robustness concerning process variations. The worst-case distance in circuit lifetime is predicted based on a new, quadratic prediction...
As semiconductor technology scales, manufacture process-related statistical variations and lifetime-dependent degradations contribute directly to the fluctuations of transistor parameters and circuit performances. Considering alone either the static process variation or the nominal lifetime degradation cannot ensure a robust design during the entire lifetime. It is thus highly necessary to obtain...
As integrated circuit technology scales down continuously, transistor parameters will shift from their nominal values due to process-induced variations and time-dependent degradations. While the former issue contributes directly to the production yield of the fresh circuit, the reliability issue will cause an additional yield loss during the lifetime. Thus the prediction of the circuit's lifetime...
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