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This paper presents an adaptive finite impulse response (FIR) equalizer with continuous-time wide-bandwidth delay line in CMOS 0.25-mum process for 2.5-Gb/s to 3.5-Gb/s data communications. To achieve wide bandwidth, fractionally spaced structure is used and an inverter with active-inductor load design is proposed as the delay cell of the tap delay line. Close loop adaptation of the fractionally spaced...
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