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Based on conventional two-step ADC principle, an 8-bit 250MSPS modified two-step ADC is proposed to reduce power dissipation. It is realized by applying triple-stage comparison for the number reduction of comparators, substituting new reference region selecting logic (RRSL) blocks for sub-DACs and adding sample/hold (S/H) circuit to replace residue amplifier. Simulated with SMIC O.35 mum/3.3 V AMS...
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