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This paper presents a 6‐bit 4 MS/s segmented successive approximation register analog‐to‐digital converter for Bluetooth low energy transceiver applications. To improve the linearity and reduce the switching power consumption, a segmented structure with new switching scheme is adopted in the capacitive digital‐to‐analog converter. The proposed switching sequence determines the MSBs according to the...
This paper proposes an 11-b 40KS/s Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) structure for sensor applications. Segmented structure is adopted in capacitive DAC to improve the linearity and decrease the power consumption. 500 aF custom-designed unit capacitors are applied in CDAC to reduce the area and to keep the INL and DNL within 1 LSB of an 11 bit ADC. A prototype...
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