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Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures such as DRAMs. DRAMs are built using minimized transistors with presumably uniform speed in an organized array structure. Process variation can introduce latency disparity among different memory arrays. With the proliferation...
The proliferation of chip multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller banks that are interconnected through packet-based network-on-chip (NoC). With increasing number of cores and cache banks integrated on a single die, the on-chip network introduces significant communication latency and power...
Proxy cache which is an important device to guarantee the quality of Web service works with a poor efficiency when hot-spot appears. To solve this problem, load balancing method should be applied. In this paper, a load balancing model based on ant colony behavior is put forward. In the model, agent monitors the status of proxy server it has been installed on. Based on that status, if it judges that...
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