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Multilevel modulation formats, such as PAM-4, have been introduced in recent years for next generation wireline communication systems for more efficient use of the available link bandwidth. High-speed ADCs with digital signal processing (DSP) can provide robust performance for such systems to compensate for the severe channel impairment as the data rate continues to increase.
This paper describes the design of a low power multi-standard transceiver in 28nm CMOS technology. Using novel circuit techniques and implementation features, the transceiver can operate at data rates of 1.2–6.8Gb/s while supporting a wide range of communication standards, including SGMII, QSGMII, PCIE, SATA, USB3, XAUI and RXAUI. Power consumption per lane is 23mW at 0.9V for SATA3 at 6Gb/s, with...
This tutorial catalogues and analyzes previously reported CMOS low noise amplifier (LNA) linearization techniques. These techniques comprise eight categories: a) feedback; b) harmonic termination; c) optimum biasing; d) feedforward; e) derivative superposition (DS); f) IM2 injection; g) noise/distortion cancellation; and h) post-distortion. This paper also addresses broadband-LNA-linearization issues...
Recent trends for A/D converters are here presented. New applications and technology scaling are the main driving forces on next generation ADCs. Adaptive ADCs and ultra-low power ADCs are motivated by new demanding specifications. Technology scaling stimulates the time-domain versus voltage-domain ADCs. Furthermore, various techniques to eliminate the power hungry opamps are in progress.
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