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Routability is one of the primary objectives in placement. There have been many researches on forecasting routing problems and improving routability in placement but no perfect solution is found. Most traditional routability-driven placers aim to improve global routing result, but true routability lies in detailed routing. Predicting detailed routing routability in placement is extremely difficult...
As a key phase of force-directed placement, cell spreading can smooth the overlap linearly by adding additional forces to shift cells to the suitable place based on the utilization of bins. However, the magnitude and direction of these additional forces is hard to be determined. Unreasonable additional forces will bring great damage to the wire length and run time. In this paper, we present a new...
As chip design complexity scales, completing routes of all nets has become a tough work under limited routing resources and increasing number of design rules. Besides, wirelength and crosstalk greatly affect the chip's performance. This paper presents a novel fine-grain track routing approach to optimize routability and crosstalk. The proposed track router is performed in a GRC-by-GRC fine-grain manner,...
Rewiring is a useful technique that perturbs the logic of Look-Up Tables (LUTs) without changing the functions of circuits. This internal logic perturbation can be used to trade for critical LUT-external logic/wire removals for EDA improvements. In this paper, we design a flow of embedding the rewiring engine into routing process for FPGA improvement. In our design, we change the priorities of target...
Boolean Satisfiability (SAT) has successfully been applied to the FPGA routing. It has many advantages over the conventional one-net-a-time routing algorithm such as routing all nets concurrently, higher flexibility and unroutability provable. However it also has the limits of scalability and is time-consuming. This paper presents some optimizations to the SAT-based routing approach by applying some...
As VLSI technology scales into sub-65 nm realm, the complexity of timing optimization is drastically increased by the consideration of power and variations. Even though designers make great efforts during physical design, they are often faced with still heavy timing violations in deep post-routing stages. For the entire design convergence and timing closure, especially under current multi-corner multi-mode...
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