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High-performance, flexible clock synthesis is a key challenge in multiple applications, from high-data-rate I/O to reconfigurable radio and radar. Conventional wireline and wireless LC-VCO based PLLs can cover a large tuning range using multiple frequency bands [1, 2], typically using a calibration loop to select an operating band for the VCO, then allowing the PLL to lock within that band. In effect,...
A key challenge in high-performance I/O, as well as in reconfigurable radio and radar applications, is the generation of a clean clock signal supporting a wide range of frequencies. The introduction of fractional-N synthesis capability for wide-tuning-range applications enables generation of arbitrary output frequencies within that range from a single choice of reference frequency. A critical challenge...
A voltage-controlled oscillator linearization technique suitable for dual-path phase-locked loops is presented. In the proposed scheme, the state of the integral control path sets the gain of a transconductor in the proportional path in such way that nearly constant VCO gain through the proportional path is achieved. A detailed analysis and design example is presented in the context of delay-interpolating...
A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. At 28 GHz the RMS jitter is 199fs (1MHz to 1GHz), phase noise is −110dBc/Hz at 10MHz offset. The 140×160µm2 32nm SOI CMOS PLL locks from...
This paper describes a new approach to low phase noise LC VCO design based on transconductance linearization of the active devices. A prototype 25GHz VCO based on this approach is integrated in a dual loop PLL and achieves superior performance compared to the state of the art. The design is implemented in the 32nm SOI deep sub-micron CMOS technology and achieves a phase noise of −130dBc/Hz at 10MHz...
As exemplified by standards such as OIF CEI-25G, 32G-FC, and next-generation 100GbE, serial link data rates are being pushed up to 25 to 28Gb/s in order to increase I/O system bandwidth. Such speeds represent a near doubling of the state-of-the-art for fully integrated transceivers [1–3]. With scaling no longer providing large gains in device speed, significant design advances must be made to attain...
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