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In this paper, a multi-view interlacing hardware architecture for High-definition (HD) (1920×1080) auto-stereoscopic 3DTV display system on a Virtex-4 FPGA is presented. Our approach focuses on the image reconstruction after DIBR, which consists of pixel rearrangement, color space conversion between RGB and YCbCr and pixel downsampling for BT.1120 HDMI format output. The FPGA hardware architecture...
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