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A low delay and speed efficient current mode Analog to Digital Converter has been described. The Analog to digital converter architecture generates 4-bit digital output in two stages. Different current comparator architectures have been used in the design and for each, the effect on the speed and area of the Analog to digital converter has been determined. Further, a power optimization technique has...
In this paper, a novel active shunt-peaked MOS Current Mode Logic (MCML) C-element for asynchronous pipelines has been proposed. The circuit is based on the technique of shunt-peaking. The proposed circuit has been developed and simulated in PSPICE using 0.18µm CMOS technology parameters. Its performance comparison with CMOS and conventional MCML C-element indicates that the proposed C-element achieves...
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