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This paper proposes a configurable logic block (CLB) for the efficient circuit realization in positive feedback source coupled logic (PFSCL) style. The proposed CLB incorporates the advantageous features of the PFSCL style and triple-tail cell concept. The operation of the new CLB is explained and the realization of different circuits by configuring the block is discussed. The efficiency of the proposed...
This paper presents a low power D-latch designed using two low power tri-state MCML buffers. The proposed D-latch consumes less power as it makes use of low power tri-state buffers which promotes power saving due to reduction in the overall current flow in the circuit during the high impedance state. The proposed low power D-latch is simulated in PSPICE using 0.18μm TSMC CMOS technology parameters...
This paper presents a MOS current mode logic (MCML) square root carry select adder (SQ-CSA) which can be used as an alternative to MCML ripple carry adder (RCA) when the number of bits in the input words is large. The proposed 16-bit MCML SQ-CSA has been implemented and simulated in PSPICE using TSMC 180 nm CMOS technology parameters. Its performance has been compared with 16-bit RCAs based on CMOS...
In this paper, a new design for current comparator based on Current Conveyor-II (CC-II) is proposed. The proposed current comparator utilizes the concept of positive feedback. Simulations have been performed on Pspice using 0.18um CMOS technology with 1.8V supply. Final results confirm a fairly quick response, less power dissipation and a resolution of 4.4uA for the current comparator. A 2-bit current...
In this paper, low-power Multi-Threshold MOS Current Mode Logic (MT-MCML) asynchronous pipeline circuits have been proposed. The circuits employ the use of multiple threshold MOS transistors to reduce the supply voltage requirement thereby decreasing their power consumption. The proposed circuits have been implemented and simulated in PSPICE using 0.18 µm CMOS technology parameters. Their performance...
A low delay and speed efficient current mode Analog to Digital Converter has been described. The Analog to digital converter architecture generates 4-bit digital output in two stages. Different current comparator architectures have been used in the design and for each, the effect on the speed and area of the Analog to digital converter has been determined. Further, a power optimization technique has...
In this paper, a new logic style named as MOS current mode logic with feedback is proposed as an alternative to conventional MOS current mode logic for implementing digital circuits operating at high frequencies. The proposed circuit style employs a positive feedback that enhances the switching speed of the circuit. The use of feedback reduces the number of transistors needed to implement the circuit...
In this paper, a novel active shunt-peaked MOS Current Mode Logic (MCML) C-element for asynchronous pipelines has been proposed. The circuit is based on the technique of shunt-peaking. The proposed circuit has been developed and simulated in PSPICE using 0.18µm CMOS technology parameters. Its performance comparison with CMOS and conventional MCML C-element indicates that the proposed C-element achieves...
In this paper, a new logic style named as MOS current mode logic with feedback (MCML-FB) is proposed as an alternative to conventional MOS current mode logic (MCML) for implementing digital circuits in wireless communication systems. The proposed circuit style combines the advantages of conventional MCML and positive feedback to improve the performance of wireless systems. The use of feedback enhances...
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