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Most VLSI watermarking techniques do not allow different authorships of multiple Intellectual Property (IP) cores to be detected directly in the field after the IPs have been integrated, fabricated and packaged into chip. Watermark inserted at the design-for-testability (DfT) stage makes its direct detection after chip packaging possible, but it protects only the downstream placement-and-routing design,...
This paper proposes an intellectual property (IP) protection scheme at the design-for-testability (DfT) stage of VLSI design flow. Additional constraints generated by the owner's digital signature have been imposed on the NP-hard problem of ordering the scan cells to achieve a watermarked solution which minimizes the penalty on power and cost of testing. As only the order of the scan cells is varied,...
This paper presents a logic re-synthesis method for embedding the IP designer information into a distributed copy of a master design that has been synthesized to meet the application constraints. Slack information of the master copy is used to identify seed cells and extract their kernels for watermark insertion at the logic synthesis level. The embedded watermark can be recovered by comparing the...
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