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A low voltage, low power CMOS delay element is proposed. With unit CMOS inverter load, the delay from 2ns to 10??s is achieved with the power consumption less than 30pW/MHz in 0.8??m CMOS technology. Based on the CMOS thyristor concept, the delay value of the proposed element can be designed in a wide range with the control current. The designed delay value is less sensitive to the supply voltage...
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