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In this paper, a new peak hold circuit which detects the top value and the bottom value of the power supply noise of a VLSI circuit is proposed. We can make a noise map by distributing the circuit over the chip and find hot-spots in which large power supply noise occurs. This circuit needs no extra clean power supply or external clock signal. Also, low power consumption can be expected because it...
Extremely high density CMOS technology for 40 nm low power applications is demonstrated. More than 50% power reduction is achieved as a SoC chip by aggressive shrinkage and low voltage operation of RF devices. Gate density of 2100 kGate/mm2 is realized by breaking down conventional trade-off of leakage power and performance with three key approaches. 0.195 mum2 SRAM with excellent static noise margin...
A 4-Gb/s, low-power, 231-1 output length, pseudo random binary sequence (PRBS) generator with a wave-pipeline technique is presented. A thirty-one stages linear feedback shift register (LFSR), whose feedback taps are connected to the first stage through EXOR, is adopted. In this LFSR, each stage consists of D-FF employing a true single phase clock (TSPC) type to increase the operating frequency. In...
A 125 MHz 1 GIPS at 1.3 V 1 W microprocessor with single-chip tightly-coupled multiprocessor architecture and low-voltage circuits is targeted to high-performance and low-power embedded systems, especially smart information terminals. This paper shows an entire chip diagram integrating four tightly-coupled processors. Each processing element (PE) is in-order two-way issue superscalar with two ALU...
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