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Concurrent interprocedural program analysis is an undecidable problem. To analysis concurrent interprocedural program, we need understand why the problem is undecidable. [1] proofs the undecidable problem via constructing a instance of PCP problem with three concurrent tasks. This paper constructs an instance of PCP problem of the concurrent interprocedural program analysis problem, but with only...
A half-rate reference-less clock and data recovery circuit is proposed, incorporating a coarse frequency-locked loop and a fine phase-locked loop with smooth switching to prevent adverse interaction and false locking. Fabricated in a 0.18-mum CMOS process, the recovered clock exhibits a peak-to- peak jitter of 60 ps for a 2-Gb/s PRBS-7 data and a phase noise of -93.5 dBc/Hz at 1-MHz offset. The core...
Decision-feedback equalization (DFE) is explored to reduce inter-symbol interference (ISI) and crosstalks in highspeed backplane applications. In the design of clock and data recovery (CDR) circuit, embedding DFE within phase and frequency detector (PFD) enhances to recover data inherently from distorted input signals and facilitates to provide DFE with recovered clock. With PRBS15 data signaling...
A clock and data recovery architecture for highspeed communication systems is proposed. Based on early-late method, the bang-bang phase and frequency detectors work in two modes: half-rate mode and quarter-rate mode, thus a large applicable data rate range is available. Simulated in a 0.18mum CMOS technology, the circuit exhibits a peak-to-peak jitter of 48ps in the recovered quarter-rate clock with...
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