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Gate-level power estimation methodologies are often considered as a sign-off level reference for digital circuit design. Nevertheless, when gate delays and related effects like glitches are taken into account, commercial state-of-the-art gate-level power estimators show surprisingly large estimation errors. Following an analysis of factors causing these inaccuracies, a novel gate-level power estimation...
Gate-level power estimation based on foundry-supplied standard cell libraries is a common analysis step during digital design. Surprisingly little is known about the accuracy of this approach and the suitability for different circuit types. At the same time, commercial tools implementing this approach are employed broadly and often regarded as the reference when comparing estimation methodologies...
In this paper, a novel adaptable reference circuit is proposed which can be used to calibrate the switching threshold of a read amplifier. The circuit is based on a network of nanoelectronic resistive switches acting as voltage dividers. In addition, active CMOS circuits are included which are used to tune the output voltage of the circuit. For the performance analysis variability models were applied...
Conductance variations in nanoelectronic resistive switches seriously affect the performance of hybrid CMOS/memristive circuits. In order to capture cycle-to-cycle variability by circuit simulation a standard model was extended for resistive switches based on the electrochemical metallization effect. The extension incorporates an additional process that simulates the randomness of the filament growth...
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