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We present a combined hardware-software based approach to scan-chain diagnosis, when the outcome of a test may be affected by system faults occurring in the logic out-side of the scan chain. For the hardware component we adopt the double-tree scan (DTS) chain architecture, which has previously been shown to be effective in reducing power, volume, and application time of tests for stuck-at and delay...
Test power, volume, and time are the major test cost parameters that must be minimized while achieving the desired level of fault coverage. Unlike prior research in delay fault testing that has focused on at most two test cost parameters, the hybrid (LOS+LOC) scheme proposed here simultaneously considers all three cost parameters and achieves better fault coverage than prior schemes, as demonstrated...
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