The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This work presents superb chip-level reliability of a BE-SONOS charge trapping NAND fabricated in both 75nm and 38nm half-pitches. Without any error correction (ECC) >;100K P/E cycling endurance for SLC and >;3K endurance for MLC are obtained using a novel non-cut SiN trapping layer. Key process integration strategies are discussed, including barrier and trapping layer engineering, p-well and...
The impact of edge fringing field effect on charge-trapping (CT) NAND Flash with various STI structures (including near-planar, body-tied FinFET, self-aligned (SA) STI, and gate-all-around (GAA) devices) is extensively studied for a thorough understanding. First, we find that the edge fringing field can cause abnormal subthreshold current during programming. Careful well doping optimization is necessary...
Although planar floating gate (FG) device using high-K IPD has been proposed, our study indicates that out tunneling through IPD due to the high electric field is inevitable, leading to programming/erasing saturation. Moreover, charge trapping in IPD is a major concern. In this work, we propose a completely different approach - using a trapping IPD for storage. Our concept is to combine the merits...
A high-performance body tied FinFET BE-SONOS device is demonstrated, suitable for NAND Flash memory scaling beyond 30 nm technology node. BE-SONOS offers efficient hole tunneling erase and excellent data retention. When integrated into a FinFET structure, a much higher program/erase speed is obtained, owing to the inherent field enhancement (FE) effect around the fin tip. In this work, a very scaled...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.