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We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Write-ability is further enhanced by an Adaptive Data-Aware Write-Assist (ADAWA) scheme. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating...
In this paper a highly flexible low power single port Static Random Access Memory (SRAM) compiler design is presented. The Divided Word Line (DWL) and Divided Bit Line (DBL) scheme were implemented for reducing active power. Particular emphasis was put to decrease standby power consumption in word line driver. The forced-stack devices as pulse generation element was introduced for sensing enable....
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