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Reconfigurable digital filter is being widely used in applications such as communication and signal processing. Its performance, power consumption, and logic resource utilization are the major factors to be taken into consideration when designing the filters. This paper proposes a concise canonic signed digit coefficient grouping method aiming at reducing the number of common subexpressions (CSs)...
Performance and power consumption are two important aspects of reconfigurable finite impulse response (FIR) filters. In this paper, a new reconfigurable FIR architecture named SCSD FIR is proposed. This proposed architecture has been synthesized in 0.13 μm technology with a precision of 16 bits. Design example shows that FIR with 551 taps achieves 21.3% area reduction and 19.0% power reduction compared...
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