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This work focuses on the timing variation-aware datapath design based on Contra-Data-Direction (CDD) clocking. Although a register assignment based on CDD clocking has been proposed, resultant datapaths suffer from the increase in registers. To overcome the problem, this paper proposes a novel timing variation-aware design using Adjustable CDD (ACDD) clocking, named ACDD-based design. An ILP-based...
This paper introduces an energy efficient acceleration technique for embedded microprocessors. By means of supporting an ALU-array based coarse-grain reconfigurable functional unit, well customized special instructions are identified and executed for each application program. Since the reconfigurable functional unit can execute several dependent instructions (a sequence of instructions), simultaneously,...
With the advance of process technologies, delay variation becomes relatively larger. As a result, it becomes difficult to improve a performance such as a clock frequency in conventional worst-case design. A post-silicon approach is one of the promising approaches to overcome this serious problem. In this paper, two techniques are introduced and combined: The first technique, named the stall insertion,...
Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations are very time consuming and need a considerable design effort. A combined analytical and simulation-based model (CAnSO*) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor...
For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. While the timing violation due to the fail of the setup constraint can be fixed by tuning a clock frequency or using a delayed latch, the timing violation...
As the feature size of transistors becomes smaller, delay variations become a serious problem in VLSI design. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. One approach to ensure the hold constraint under delay variations is to enlarge the minimum-path delay between registers, which is called minimum-path...
Application-specific instruction set extension is an effective technique for reducing accesses to components such as on- and off-chip memories, register file and enhancing the energy efficiency. However, the addition of custom functional units to the base processor is required for supporting custom instructions, which due to the increase of manufacturing and design costs in new nanometer-scale technologies...
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