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Significant stress is induced in the crystalline Si area around a Cu-filled Through Silicon Via (TSV) due to the large mismatch in the co-efficient of thermal expansion (CTE) between Si and Cu. As a result, CMOS devices fabricated within the stressed Si region will show undesired variations in their electrical performance. This paper reports a novel method to isolate the TSV-induced stress from active...
Transient responses of 3D stacked-die package with through silicon via (TSV) structure under board level drop test load following the JEDEC standard are investigated using the Input-G finite element simulation method. In order to reduce the finite element mesh size the stacked-die package under investigation is modeled with details while the others are simplified as blocks with equivalent material...
Analytical solution is established to calculate equivalent thermal resistances of the through silicon via (TSV) structure in both z direction and x y directions and is verified by the finite element simulation. The effects of the structural parameters such as the thickness of die, the diameter of copper via and the pitch of the copper via on the equivalent thermal conductivity of composite TSV structure...
A finite element model which includes electromigration, thermomigration, stress migration and concentration diffusion is established to study the mass diffusion phenomenon. Numerical experiment is carried out to obtain the electrical, thermal, stress and atomic concentration fields of the sweat and through silicon via (TSV) structure under high current density load. The effectiveness of the electromigration...
A finite element model which includes fluid flow, transport by diffusion, migration and convection, multiple species, and reactions is established to simulate the copper electrochemical deposition process in through silicon via (TSV) trench. The effects of fluid flow of the bulk copper electrolyte on the micro TSV trench have been investigated. The copper plating process in different TSV trench geometries...
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