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In this paper we propose a novel approach for designing digital circuits that uses the variance of a signal to represent Boolean logic levels. The variance-based logic (VBL) representation enables embedding of rectification and multiplication modules within the basic logic cells and unlike AC-coupled or energy-recovery logic circuits the proposed approach obviates the need for any phase synchronization...
This paper tries to do the research of analyzing the relation of the customer trust, the customer satisfaction and purchase intention under the electronic commerce shopping environment. Drawing on the theory of customer trust, customer satisfaction and purchase intention, based on a survey of 102 respondents from the University in China, the United Kingdom, and the United States, the results showed...
A battery-powered aerial microrobotic System-on-Chip (SoC) has stringent weight and power budgets, which requires fully-integrated solutions for both clock generation and voltage regulation. Supply-noise resilience is important yet challenging for such SoC systems due to a non-constant battery discharge profile and load current variability. This paper proposes an adaptive-frequency clocking scheme...
In this paper, we present two implementations of a closed-loop process compensation scheme for high speed ring oscillators-the comparator based and the switched capacitor based loops. We provide detailed discussion of the frequency accuracy, loop stability, and implementation cost for each design. More than 150 test chips from multiple wafer-runs in a 90 nm CMOS process verify that frequency accuracy...
A 3-stage current-starved ring oscillator with 65.1% reduction in process variation in a 90 nm CMOS process is presented. The low variation is achieved without degrading the mean operating frequency through the implementation of an addition-based current source to replace a single transistor current source in each inverter stage. No post-fabrication trimming or calibration is required. Circuit simulations...
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