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The high voltage device can be embedded into conventional shallow trench isolation (STI) logic process. Basically, SVX (Smart Voltage Extension) technique was applied in order to integrate 32 V high voltage LDMOS into a standard 0.18 micron low voltage CMOS technology without any process change. However, a double hump issue was being observed in high voltage LDNMOS. The double hump phenomenon is mainly...
In this paper, a 40 V versatile HV LDMOS technology with lower Rdson has been developed in the existing 0.18 mum LV CMOS process. The HV LDMOS are designed by using DOE concept on the simulation results from T-supreme followed by Medici. The process complexity to incorporate the HV kept as simple as possible which does not affect much due to baseline. DOE model are constructed from both the critical...
Designing of high voltage LDMOS with a reduced surface field (RESURF) structure have been investigated to achieve the optimum figure of merit, maximum breakdown voltage accompanied with low on resistance. The drift region profile and device geometry plays important role to achieve target breakdown voltage of 80 V. The electrical behaviors of the designed high voltage LDMOS for both on state and off...
Rapid increasing demand towards high voltage MOSFETs device integrated in low voltage CMOS analog and digital circuits for automobile and power management application has driven the development of 0.18 um high voltage lateral diffused MOSFET (LDMOS) which capable to have 80 V breakdown voltage. During designing this high voltage LDMOS, it is observed that the device performance is very dependent towards...
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