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We have previously proposed a new digital CMOS circuit which combined subthreshold circuit and adiabatic logic circuit with ultra-low power consumption. Our proposed circuit which is driven by two AC power supply with different frequency and amplitude, and is adapted to be provided a margin of switching timing of input signal. In this paper, we show a skew tolerance analysis of subthreshold adiabatic...
We investigate our previously proposed charge sharing symmetric adiabatic logic, which was designed to thwart differential power analysis (DPA) attack. The ability of the logic to withstand DPA attacks is analyzed from the variations in the transitional power consumption of individual logics and in the bit-parallel cellular multiplier over GF(2m). Then, we compare the results with those of the previous...
The Japanese Quasi-Zenith Satellite System (QZSS) offers the possibility to transmit information with an unprecedented bit rate of 2000 bps via the L-band experimental signal. This feature can be used to disseminate Japan Standard Time, i.e., Universal Time Coordinated (UTC)(NICT), to any user capable of receiving the new QZSS signal. Various timing transmission modes as well as a dedicated ionosphere...
This paper reports a comparison of energy dissipation between different adiabatic logics in the subthreshold operation. In SPICE simulation we use a real industrial 0.18 μm BSIM3v3 model having a device parameter in the subthreshold region and then confirm the energy savings of quasi-adiabatic logic families, namely, 2N2N2P, 2PC2AL, CAL, ECRL, PAL, PECRL, PFAL, and SAL. From the results we show that...
Multi-Sites Test is the popular way to reduce the cost-of-test (COT) at the wafer and the final test. Limitations exist, however, such as the low Multi-Site Efficiency of analog mixed signal tests and the high system price for large pin count devices. Concurrent Test has been implemented to reduce the test time. This test strategy is difficult to implement without the DFT design of the device. The...
This paper presents the simulation results of a 4×4-bit array two phase clocked adiabatic static CMOS logic (2PASCL) multiplier using 0.18 µm standard CMOS technology. We also propose a new design of 2PASCL XOR which reduces the number of transistors as well as the power consumption. Analytical method to compare the lower current flow in adiabatic circuit is also presented. At transition frequencies...
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