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HV n-/p-LDMOS devices with the source-side extending into bulk-region to evaluate the electrostatic-discharge (ESD) protection robustness by a TSMC 0.25 µm 60 V process are investigated in this paper. After a systematic analysis, the trigger voltage (Vt1) values of the n-LDMOS with the source-side extending into the bulk-end either by uniformly or non-uniformly distributed manners that had decreased...
The pLDMOS related devices fabricated by a TSMC 0.25 µm 60 V process was investigated in this paper. For the ESD improvement, some DUTs inserting the N+ zone to form an embedded SCR in the drain end or guard-ring area, respectively. From the TLP testing results, the It2 values of the drain parasitic SCR npn-type and pnp-type could reach > 7 A, higher than that of the traditional pLDMOS device....
The impacts of current-path variation on the ESD robustness of nLDMOS devices as the drain-side modulation by a 0.18 μm/40 V process are evaluated in this paper. From the transmission-line-pulsing (TLP) measurement, the secondary breakdown current (It2) of an nLDMOS with the drain-side embedded SCR structure & "pnp" arrangement (DUT-2) increased from 2.498 A up to > 7 A (at least...
Single-stage high-order delta–sigma modulators (DSMs) designed by methods with root loci inside the unit circle (RLiUC) can operate stably with full-scale input. The previously published RLiUC method uses a conservative approach to design the loop filter's transfer function of a DSM, thus resulting in a modest SNR. In this brief, the pole–zero locations of are optimized to maximize the...
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