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The performance and reliability of ZrO2/In0.53Ga0.47As MOSFETs are shown to be improved by simultaneous reduction of dielectric and interface charges. An amorphous (La)AlOx interlayer at the ZrO2/In0.53Ga0.47As interface is a key to reduce border traps, interface traps and move ZrO2 fixed charge away from the In0.53Ga0.47As. Border traps are reduced ~3x, effective fixed charges are reduced ~3x and...
We demonstrate for the first time molybdenum based oxygen-bearing electrodes for improved performance in MANOS (Metal-Alumina-Nitride-Oxide) charge-trap NVM, and also MIM-DRAM type devices. The meta-stable high work- function (Wfn) molybdenum-oxynitride (MoON) electrodes result in improved retention and erase saturation for the charge trap NVM devices and improved leakage for the MIM devices. Although...
We demonstrate for the first time improved program, erase, and endurance for charge trap flash TaN-Al2O3-Si3N4-ldquoTunnel-oxide (TO)rdquo-Si MOSFETs through band engineered tunnel oxides (BETO). Several high-K dielectrics (HfO2, HfSiO, Al2O3, Si3N4) and tunnel stack sequences (SiO2-high-k, SiO2-high-k-SiO2) are compared. New results are as follows: SiO2/Al2O3 (OA) BE-TO and SiO2/Si3N4/SiO2 (ONO)...
Gate first 0.59 nm EOT HfOx/metal gate stacks for 16 nm node application are demonstrated for the first time. By controlling O during HfOx deposition, ldquozerordquo low-k SiOx interface (ZIL) forms despite a 1020degC activation anneal. This 0.59 nm EOT is a 30% improvement over a state of the art 32 nm HK/MG technology. We compare and demonstrate for the first time the improved scalability of ZIL...
Through a detailed evaluation of various dielectrics, we address the primary challenges associated with gate stacks on high electron mobility InGaAs channels. More specifically we address key gate stack issues including a) EOT scalability for high performance and electrostatic control (this work CET ~0.78 nm) with acceptable leakage both at operating and offstate for low power (this work Jg ~1 A/cm...
For the first time, we provide mechanistic understanding of high gate leakage current on surface channel SiGe pFET with high-k/metal gate to enable sub 1 nm EOT. The primary mechanism limiting EOT scaling is Ge enhanced Si oxidation resulting in a thick (1.4 nm) SiOx interface layer. A secondary mechanism, Ge doping (ges4%) in high-k, possibly by up diffusion, also results in higher leakage. With...
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