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The electron and hole injection statistics of BE-SONOS NAND Flash is studied for the first time using a 75 nm charge-trapping NAND Flash test chip. By using the incremental step pulse programming (ISPP) method the impact of device variations are minimized and the electron number (N) fluctuation can be identified. We find that both electron and hole injection statistics well follow the Poisson statistics...
Floating gate (FG) devices using barrier-engineered (BE) tunneling dielectric have been studied both theoretically and experimentally. Through WKB modeling the tunneling efficiency of various multi-layer tunneling barriers can be well predicted. Experimental results for FG devices with oxide-nitride-oxide (ONO) U-shaped barrier are examined to validate our model. Furthermore, a large-density array...
A vertical channel SONOS memory, which is compatible with current CMOS process and has four physical storage nodes per unit area, is fabricated and electrically evaluated. Comparing with a planar device, the array cell tuning is much easier since the channel length is no longer limited by array area. After reviewing key performances including program/erase (P/E) speeds, second bit effect, program...
Gate stack etch profile-induced reliability issues are reviewed and discussed. A taper nitride profile, which blocks source/drain (S/D) implantation, induces an unwanted n- region. In other words, residual charges above the junctions can deplete the n- much easily and cut off the channel formation. This will cause poor string resistance distribution, worse endurance behavior, program and erase (P/E)...
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