The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The adder circuit is used as a main component in the multiplier circuits. The Baugh-Wooley, Braun and CSA multipliers are designed by using our proposed adder cell. The proposed adder circuit is designed by using Shannon theorem. The multiplier circuits are schematised by using DSCH2 VLSI CAD tool and their layouts are generated by using Microwind 3 VLSI CAD tool. The proposed adder based multiplier...
The minimization of logic gates is needed to simplify the hardware design area of programmable logic arrays (PLAs) and to speed up the circuits. The VLSI designers can use minimization methods to produce high speed, inexpensive and energy-efficient integrated circuits with increased complexity. Quine-McCluskey (Q-M) is an attractive algorithm for simplifying Boolean expressions because it can handle...
This paper presents an error tolerant hardware efficient VLSI architecture for bit parallel systolic multiplication over dual base, which can be pipelined. This error tolerant architecture is well suited to VLSI implementation because of its regularity, modular structure, and unidirectional data flow. The length of the largest delay path and area of this architecture are less compared to the bit parallel...
In this paper we have analyzed an 8-bit multiplier circuit using non clocked pass gate families with help of carry save multiplier (CSA) technique. The multiplier cell of the adder is designed by using pass transistors (n-transistors), p-transistors used as cross-coupled devices. The adder cell is designed by using multiplexing control input techniques. A combination of n- and p-transistors used on...
It is known that ramp-based models are not sufficient for accurate timing modeling. In this paper, we develop a technique that accurately models the waveforms, and also allows a flexible trade-off of accuracy vs. computational and representational cost. The technique is based on singular value decomposition (SVD) and it naturally leads to a more general gate delay model which can be applied in any...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.