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This paper covers the design of dynamic element matching algorithms for the compensation of output level mismatch in the internal DAC of a ΣΔ modulator. This issue is considered from the definition of the algorithm itself, down to the design at the transistor level in a scaled CMOS technology. Indeed the main focus of the paper is to demonstrate that the hardware complexity is a major element to be...
Direct injection locking applied to a ring oscillator results in a divide-by-7 frequency divider circuit with a 22% locking range, from 4.1 to 5.1 GHz. The 38 × 31 μm2 65 nm CMOS prototype draws 430 μA from a 1.2 V supply. The output phase noise tracks the reference's one with the expected 17 dB difference at small offsets, settling to a -133dBc/Hz floor at larger offsets. The integrated rms jitter...
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