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This paper presents a 5GS/s 12-way 10b time-interleaved SAR ADC. Each SAR sub-ADC resolves 11b using reduced radix-2 with 1b redundancy, which tolerates decision errors arising from noise, reference settling error, etc. The top-plate sampling with merged capacitor switching algorithm is applied to achieve high switching efficiency, small area and less comparator noise. Several design techniques for...
In this paper, a low power 6-bit ADC that uses reference voltage and common-mode calibration is presented. A method for adjusting the differential and common-mode reference voltages used by the ADC to improve its linearity is described. Power dissipation is reduced by using small device sizes in the ADC and relying on calibration to cancel the large non-ideal offsets due to device mismatches. The...
A low power 6-bit ADC that uses reference voltage and common-mode calibration to improve linearity and reduce power dissipation is presented. The ADC occupies 0.13 mm2 in 65 nm CMOS. The ADC dissipates 4 mW at 100 MS/s and 12 mW at 800 MS/s from a 1.2 V supply.
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