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As the enabling technology, virtualization plays an important role in cloud computing by providing the capability of running multiple operating systems and applications on top of the same underlying hardware. Early detection of vulnerability in virtualization is vital for virtualization performance and to protect against attacks that may lead to information leak or virtual machine(VM) escape. While...
Aiming at the attitude stabilization and angle tracking control of quadrotor aircraft, an optimized cascade double-loop PI-PID controller is proposed. It is based on strong coupling and nonlinear dynamic model in this paper. A PI controller acts as an outer loop controller, which controls primary physical parameter, namely the attitude. The other PID controller acts as an inner loop controller, which...
This paper proposes the concept of application software compatibility and highlights its important implication to high-reliable information application system. Aiming at the issues of typical of software compatibility, an analysis method of software compatibility is presented based on hardware virtualization. Compatibility of two typical information security software is analyzed and the results are...
This paper presents three pause mechanisms of multithreaded processors (micro-engine) of network processor, which is mainly used for dealing with reference instruction. We implement design of RTL-level code, functional simulation and logic synthesis on these three mechanisms. At last according to frequency and hardware resources and the expected performance requirements we select pause method based...
High performance routers require fast packet buffers to hold packets awaiting transmission[1]. These buffers usually use a memory hierarchy that consist of expensive but fast SRAM and cheap but slow DRAM to meet both, speed and capacity requirements[2]. In this paper, we introduce a particular memory hierarchy as packet buffer architecture which consists of multiple, independent memory channels of...
The traditional hardware description languages (VHDL and Verilog) is not suitable for system-level modeling and Hardware Software Codesign, while the SystemC language is more suitable than the traditional HDL language for system-level modeling. This paper describes the packet processing engine(PPE) characteristics of XDNP network processor, analyze the advantage of system-level modeling in SystemC...
The study in this paper is aimed at improving the performance of a network processor design (XDNP) based on a Virtex-4 FPGA by using the PlanAhead tool offered by XILINX. PlanAhead gives a unique visibility into the design. The tool can very quickly identify the critical path, and then supply hierarchical floorplanning to achieve faster timing closure. XDNP is targeted at networking applications requiring...
In this paper a multithreaded processor with hardware context switch mechanism driven by external events is presented for multi-processor system on chip (MPSoC). Combining this mechanism with asynchronous memory access the proposed processor implements Non-preemptive thread scheduling which can assure fairness of threads and optimization for single thread. The overhead of hardware thread switch is...
Search and rescue robots can benefit from small size as it facilitates access to voids and movement in cramped quarters. Yet, small robots cannot be the entire answer for urban search and rescue because small size limits the size of actuators, sensor payloads, computational capacity and battery capacity. Nonetheless, we are attempting to alleviate these limitations by developing the hardware and software...
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