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This paper deals in waveform analysis, crosstalk peak and delay estimation of a CMOS gate driven capacitively and inductively coupled interconnect for simultaneously switching inputs. A transmission line based coupled model of interconnect is used for analysis. Peaks and delays at far-end of victim line are estimated for the conditions when the inputs to two coupled interconnects are switching in-phase...
Long interconnects in very large scale integration (VLSI) circuits result in high delays and power dissipation, thereby degrading the performance of an integrated circuit. The feasibilities of minimizing both delay and power dissipation in long interconnects by insertion of voltage-scaled repeaters have been explored in this paper. The results show a decrease in optimum number of repeaters with voltage-scaling,...
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