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Strained Si is implemented into the standard CMOS process to enhance carrier transport properties since the 90 nm technology node. However, due to the non-uniform stress distribution in the channel, the enhancement of carrier mobility and threshold voltage strongly depend on layout parameters, such as channel length (L) and source/drain diffusion length (Lsd). In this work, a compact model that physically...
This paper presents design and modeling techniques for integrated passive devices (IPDs) that can be stacked with RF chips in a highly integrated three-dimensional IC for wireless applications. The research starts to study winding and modeling techniques for high-efficiency planar transformers. In an Above-IC process for silicon IPDs, the planar transformers realized can provide a passive efficiency...
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