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The impact on the reliability of capping layers for low Vt nMOS and pMOS high-k transistors with metal gate is investigated and devices without the resist and strip process are compared to different resist removal recipes. It is found that the interface is not affected by the cap layer, but during the resist removal a thin defect layer is created. While with the cap above the host dielectric the impact...
We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by...
The scalability of Ni fully silicided (FUSI) gate processes to short gate lengths was studied for NiSi, Ni2Si, and Ni31 Si12. It is shown that the control of the deposited Ni-to-Si ratio is not effective for phase and Vt control at short gate lengths. A transition to Ni-richer phases at short gate lengths was found for nonoptimized NiSi and Ni2Si processes with excessive thermal budgets, resulting...
We report record unloaded ring oscillator delay (17ps at VDD = 1.1V and 20pA/mum Ioff) using low power CMOS transistors with Ni-based fully silicided (FUSI) gates on HfSiON. This result comes from two key advancements over our previous report presented in A. Lauwers et al. (2005). First, we have improved the (unstrained) devices Idsat to be 560/245muA/mum for nMOS/pMOS at an Ioff = 20pA/mum and V...
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