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This paper proposes closed-form expressions of parasitic parameters in a silicon substrate that consider substrate contacts. In general bulk CMOS technologies, the standard cells with bulk (substrate and well) contacts or tap cells for bulk contacts are used in physical layout designs. As tap cell placement methods, there are dense random placements and sparse regular placements in cell rows vertically...
We propose a model for coupling that considers substrate contacts between through silicon vias (TSVs) in bulk-CMOS technologies. The proposed model is compact but has reasonable accuracy for the dense substrate contacts in large-scale three dimensional integrated circuits (3D ICs). We describe the modeling for substrate contacts with the equivalent electrical circuit, discuss the impact of substrate...
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