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In this work, the power-rail ESD clamp circuit fabricated in 130 nm CMOS process is investigated. In order to improve the ESD protection ability, the power-rail ESD clamp circuit with gate-substrate-triggered is proposed. By comparing with the other two techniques, gate-driven and substrate-triggered, it is shown that the secondary breakdown current of the power-rail ESD clamp circuit with gate-substrate-triggered...
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