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This paper propose an efficient interconnect interface, which has been applied in reconfigurable multimedia system (REMUS). In order to achieve high performance of data share between multi cores, this interconnect interface applies overlapping operation mechanism in memory. Test of H.264 HiP (High Profile) decoding shows that the data exchange rate achieves a speedup of 285% compared with the AHB...
This paper implements a fast complete deblocking filter on a novel coarse-grained reconfigurable processor, REMUS (REconfigurable Multimedia System). Reconfigurable processors have been proved to be the potential candidates for multimedia processing. However, their weakness in processing control-intensive tasks becomes a bottleneck in many reconfigurable applications. Mapping control-intensive tasks...
Computing-intensive algorithms which occupy most of executing time are always the main bottleneck in real-time or high quality video applications. In this paper, the optimization methods of the computing-intensive decoding algorithms of H.264, including MC (Motion Compensation), Deblocking and IDCT-IQ (Inverse Discrete Cosine Transform-Inverse Quantization), are proposed firstly, and then implemented...
This paper proposes a reconfigurable multi-processor SoC for media applications called REMUS (REconfigurable Multi-media System), which consists of 512 processing engines and two ARMs. The processing engines are divided into two dynamic configuration groups, which can be easily tailored and extended. The processing engines, DBIs (Data Buffering Interface, DBI) and context interfaces build up a large...
This paper proposes a novel technique of contexts (configure information) switch scheme in the loop pipeline, which effectively reduces the reconfigure time and speedup the application. The target architecture is an embedded coarse-grained reconfigurable processor, which consists of a general processor and a coarse-grained reconfigurable cell array (RCA). The technique focuses on the kernel loop body...
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