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A built-in self-test (BIST) for testing high speed source-synchronous memory interfaces has been designed using 0.18-μm TSMC process. To overcome limitations of the resolution and the accuracy in low-cost automated test equipment (ATE), a cycle-by-cycle controllable embedded pattern generator in the proposed BIST scheme is presented to specify performance-related I/O parameters. Using this method,...
This paper presents a Built-In Self-Test (BIST) circuit for high speed I/O, based on an embedded pattern generator to remove external factors which could affect the I/O parameters. The rising and falling edge positions of the generated patterns can be controlled independently during every cycle. In the basic operation mode, ATE provides the codes for controlling the edge positions, while in extended...
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