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Clock distribution networks consume a significant portion of total chip power in high-performance designs. Resonant clocks are one proposed method to lower this power in modern designs as well as a fewer required clock buffers. Recent resonant solutions are limited to optimal performance at one particular frequency which is problematic since dynamic frequency scaling is often used to lower overall...
Distributed-LC resonant clock distribution is a viable technique to reduce clock distribution network (CDN) dynamic power. However, resonant clocks can require significant on-chip resources to form the inductors and decoupling capacitors which discourages adoption. This paper uses a compensation capacitor (Cc) to reduce the overhead of the on-chip inductor and capacitor resources without changing...
In this paper, the system application, the structure and the duties of the dc breakers are firstly introduced, and then the test principle of the dc breakers is told. Based on that, the test circuits model is established and the simulation analysis of the broken process is made for passive dc breakers by the PSCAD/EMTDC simulation software. The breaking test is made on the dc breakers prototype, and...
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