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A virtual channel (VC) calculation algorithm for wormhole-switched on-chip networks is proposed. Traditionally, the virtual channels were allocated uniformly, which results in a waste of area and power. To remedy this situation, based on the queuing theory, we propose a router analytical model. Using this model, the proposed algorithm calculates the bandwidth usage at each router in the network according...
A new deadlock-free dynamic routing algorithm is proposed for wormhole-switched network-on-chip. Introducing the concept of multilevel congestion-aware mechanism which conveys more accurate feedback information about network congestion status than the DyAD routing, the proposed algorithm adopt proper routing algorithm to forward packets according to the current congestion level. Simulation results...
This paper develops a novel reconfigurable architecture, CMOS-nanorelay FPGA (cFPGA) by integrating carbon nanorelays with CMOS devices to function as FPGA components. cFPGA is a highly efficient architecture, providing 2X density and standby power improvement along with a 30% dynamic power reduction as compared with solely CMOS FPGA circuits. This performance improvement is achieved by using 2T1N...
This paper introduces a novel CMOS-memristor hybrid reconfigurable architecture, mFPGA. Different from the existing crossbar-based CMOS-memristor architectures, mFPGA mainly consists of lTlM-like structures that can be fabricated by using a CMOS-compatible process. These devices can efficiently establish FPGA block memories. More importantly, novel CMOS-memristor routing switches are developed to...
A concentrator-based load balancing multi-path self routing switching fabric(LB-MPSR-C) was proposed recently, which was based on sorting concentrators, load-balanced and Birkhoff von-Neumann switching theory. This structure can achieve 100% throughput under admissible traffic pattern, its scalability for super large scale switching system and property of lowest hardware complexity have been deeply...
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