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The performance degradation resulting from the addition of ESD protection devices to very high speed Analog/RF designs is the main reason for low ESD robustness in these applications. This paper introduces an ESD methodology that combines device development and characterization as well as simulation, for high speed Analog/RF products. In this work a special ground referenced ESD network is introduced...
A flow and a CAD tool for the simulation of the ESD CDM classification test event in SPICE is described. The methodology consists of deconstructing the CDM test into its relevant components. The modeling and calibration of each component is shown to be essential in the development of a generic simulation approach predicting CDM pass and fail levels. The successful implementation of the flow is demonstrated...
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