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Null convention logic units are the most important logic units in asynchronous circuits. This paper proposes a new realization of null convention logic unit based on semi-static threshold gates. Through adding a cutoff transistor into the pull-up path, the leakage current can be greatly decreased, which can resolve the issue of leakage current increment in deep submicron technology. Comparisons are...
This paper proposes a novel low-power fully asynchronous ACS module of the Viterbi decoder to improve the shortcomings of low throughput and high power consumption in conventional synchronous ACS module. The computation quantity can be reduced by adopting pre-computation algorithm which can select the survival path ahead of time. We use null convention logic to implement the fully asynchronous circuits...
This paper proposes four low power adder cells using different XOR and XNOR gate architectures. Two sets of circuit designs are presented. One implements full adders with 3 transistors (3-T) XOR and XNOR gates. The other applies Gate-Diffusion-Input (GDI) technique to full adders. Simulations are performed by using Hspice based on 180 nm CMOS technology. In comparison with Static Energy Recovery Full...
Through the research on charge redistribution SAR A/D converter, three energy-efficient capacitor arrays are discussed in this paper. The switching energy of the traditional architecture, charge sharing architecture, capacitor splitting architecture and two-step architecture capacitor arrays is derived and analyzed. Based on SMIC 65 nm CMOS process, 10-bit SAR A/D converters of all these architectures...
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