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This paper presents the design and verification of a proposed 30-GHz power-efficient phase-locked loop (PLL) frequency synthesizer for 60-GHz applications. Fabricated by a commercial 0.18-$\mu \text{m}$ SiGe BiCMOS process, the synthesizer employs coupled LC tank voltage-controlled oscillator, high power-added efficiency amplifier, reconfigurable divider realizing fractional division ratios for...
This paper presents a multi-mode power efficient PLL synthesizer with low power consumption and low phase noise using coupled-tank voltage controlled oscillator and local oscillator chain for 60 GHz transceiver supporting IEEE 802.11 ad standards. Fabricated in commercial 0.18 µm SiGe BiCMOS process with a single 1.8 V supply, the PLL synthesizer covers frequency from 29.5 GHz to 33.5 GHz with a RMS...
The beam forming at millimeter-wave for commercial standards like IEEE 802.11ad, is drawing much attention recently. Despite its advantages of high gain, beam-steering capability, and wide spatial coverage, phased-array requires power-hungry and costly multiple channels, especially in large-scale array systems. Thus, it becomes crucial to develop low power and compact circuits for the systems to be...
This paper presents a novel 24/36-GHz double conversion heterodyne architecture for IEEE 802.15.3c (60-GHz) applications. The selection of the first local oscillator frequency as 36-GHz gives rise to an intermediate frequency that yields significant cost advantage by reusing the 24-GHz architecture adopted by the automotive industry for both the receiver and transmitter second stage frequency translation...
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