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A novel 10 Gbit/s source-series-terminated (SST) transmitter in 65 nm CMOS technology is presented. Different from the conventional SST transmitter with the swing fixed to the supply voltage, the proposed transmitter, employing modified SST topology with switch-based shunting legs, achieves tunable swing to provide suitable a output voltage for specific channel loss, resulting in higher power efficiency...
This paper presents a 2-tap 40-Gb/s 4-PAM transmitter with level selection based pre-emphasis. The parallel input to the transmitter is pre-coded at low frequencies, so that the pre-emphasis tap injects different currents into the output node of the transmitter based on different level changes of the output signal. The proposed pre-emphasis suppresses overshooting and lowers power consumption. The...
A novel half-rate source-series-terminated (SST) transmitter in 65nm bulk CMOS technology is presented in this paper. Compared to previous half-rate SST transmitters, the proposed one consists of four binary-weighted slices increasing proportionally as 1x, 2x, 4x and 8x and the range of pre-emphasis level is increased greatly by the clock-match block to adapt to different channel. The half-rate transmitter...
A 65 nm CMOS 20 Gb/s transmitter with a low-voltage differential signalling (LVDS) driver is presented. A novel power-efficient pre-emphasis method that eliminates power wasting in conventional pre-emphasis is proposed. The input to the driver is pre-coded so that the pre-emphasis taps only inject current to the output nodes upon voltage level transition of the output signal. Current does not flow...
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